The present invention relates to a non-volatile semiconductor memory device and a manufacturing method thereof, and more particularly, to a non-volatile semiconductor memory device having a selective transistor having a butted contact structure and a manufacturing method thereof.
In data processing systems, the information storage apparatus is of much significance. The semiconductor memory devices are classified into a volatile memory device which loses the contents of the memory if power is not supplied and a non-volatile memory device which holds the contents even without a supplied power. However, non-volatile memory devices have limited application because its contents cannot be easily altered, as well as having other operational difficulties.
However, non-volatile memory devices adopting a MOS floating-gate structure have been widely used. Such devices utilize floating gates made of conductive material which is electrically isolated from the semiconductor substrate. Here, since the gate is capacitively coupled with the semiconductor substrate, it forms a MOS transistor for sensing the charged state of the floating gate. The MOS transistor is in either a conduction state ("ON") or a non-conduction state ("OFF") according to the presence or absence of floating gate charges, so as to store logic bits "1" or "0". As the mechanism for applying such charges to the floating gate, and their removal, hot electrons produced by avalanche breakdown and tunnelling effects have been used.
Among such non-volatile semiconductor memory devices, demand has increased for electrically erasable & programmable read only memories (EEPROMs) which electrically store and erase the data.
The structure of the conventional EEPROM cell, as disclosed in "ISSCC 82, National Semiconductor" (page 108, 1982) and "IEEE Electron Devices" (page 1178, 1982) is described below with reference to FIGS. 1 and 2. Here, FIG. 1 shows a planar structure of the cell and FIG. 2 shows a vertical structure of the cell.
The cell of the EEPROM in which two transistors form a single cell (shown as a dotted line in FIG. 1). comprises a select transistor 3 which is used for selecting the cell and a storage transistor 4 which plays the roll of storing electrons in a floating gate. As shown in FIG. 2, in the cell structure of the conventional EEPROM, the gate of the select transistor is formed as a second conductive layer for forming a control gate which is formed on the floating gate of the storage transistor composed of a first conductive layer. Also, a buried N.sup.+ layer 5 is formed below a tunnel oxidation film 2 which causes tunnelling to occur when the programmed data is erased.
Operation of the EEPROM cell formed as above is described below with reference to an equivalent circuit diagram of the cell shown in FIG. 3.
When the programming of the cell is erased, a high voltage of 15 V to 20 V is applied to a control gate C/G of storage transistor 4, and a proper voltage is applied to a select gate S/G of select transistor 3. By doing so, if a bit line voltage of 0 V is applied to the buried N.sup.+ region, the electrons are charged in the floating gate by means of tunnelling electrons resulting from the strong electric field between the floating gate and the buried N.sup.+ region.
Cell programming is performed as a result of the tunnelling of the electrons of the floating gate due to high voltage applied to the buried N.sup.+ region by applying 0 V to control gate C/G and applying a high voltage of 10 V to 20 V to the bit line and select gate S/G of the select transistor.
By repeating an operation such as that described above, the cell in which data is programmed or erased is read by a sensing amplifier for sensing the current passing through the bit line according to the presence or absence of the electrons in the floating gate, with 1-3 V applied to the bit line, Vcc supplied to the select gate and 2-3 V applied to the control gate.
As described above, for EEPROM cell programming, since high voltage is applied to the bit line, two transistors constitute a single cell and a tunnelling region is required, the application of such cells is difficult in high integration density. Here, the limitation of cell integration is primarily due to the tunnelling region being formed inside the floating gate. Another limiting factor is that the buried N.sup.+ region must be formed so as to match the tunnelling region. Since the gate of the select transistor is formed of the second conductive layer, the floating gate of the storage transistor is formed of the first conductive layer. Thereafter, when the gate of the select transistor and the control gate of the storage transistor are formed of the second conductive layer, the etching process of the second conductive layer should be taken into consideration. Accordingly, the distance between the select transistor and the storage transistor increases beyond the photolithography limitations, which also leads to difficulty in realizing high integration. Also, the floating gate formed of the first conductive layer is misaligned with the control gate formed of the second conductive layer.